Digital System Test And Testable Design: Using ... -

Scan architectures, RT-level scan design, and Boundary Scan (JTAG).

This book is widely used as a primary text in and Design for Testability courses. More information can be found at Springer Nature or through retailers like Amazon .

The text treats testing and testability as integral parts of the digital design process rather than afterthoughts. Digital System Test and Testable Design: Using ...

It utilizes Verilog models and testbenches to implement fault simulation and test generation algorithms.

The book describes on-chip decompression algorithms in Verilog, providing a realistic look at how these impact overall chip area and performance. Key Technical Coverage Scan architectures, RT-level scan design, and Boundary Scan

A distinguishing feature is the extensive use of the Verilog Programming Language Interface (PLI) . This allows for a mixed hardware/software environment where users can develop "virtual testers" to evaluate complex test strategies.

Memory fault models, MBIST (Memory BIST) methods, and functional procedures. The text treats testing and testability as integral

Are you interested in a specific from the book, like BIST or Boundary Scan , for a more detailed breakdown? Courses Syllabus – Monsoon 2024 - pgadmissions@iiit.ac.in